Flemming Andersen

 Flemming Andersen

Flemming Andersen

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Biography

Texas A&M University College Station - Computer Science


Resume

  • 1987

    Tele Danmark

    TeleDanmark Research/Computer Science

    Galois

    Inc.

    Texas A&M University

    Computer Science and Engineering

    TeleDanmark/Research & Development

    Researcher

    Portland

    Oregon Area

    Being able to use my expertise and experience in formal methods- and verification of concurrent systems as well as hardware systems

    I am excited to be working at Galois in the DARPA SSITH program developing formal methods- and tools in addition to applying formal verification tools to detect security vulnerabilities in hardware and concurrent software.

    Research Engineer

    Galois

    Inc.

    Responsible for developing new technology to efficiently formal verification of the floating-point- and integer arithmetic of Intel's vector processing units to avoid a repeat of the 1994 FDIV bug that coast Intel almost $500 million.

    Intel/Visualization Group

    Responsible for the development of new internet services

    among which were the Danish Yellow pages

    a Skype like Internet phone service

    and streaming video like youtube

    Project Manager

    Copenhagen Area

    Denmark

    Tele Danmark

    Develop formal methods and systems for telecommunication systems

    TeleDanmark Research/Computer Science

    Intel

    Management

    research

    and development of new formal methods and tools to verify critical components of many core processors including protocol components and vector processing with floating-point arithmetic.

    Principal Engineer and Formal Verification Manager

    Portland

    Oregon Area

    College Station

    Texas

    Texas A&M University

    Computer Science and Engineering

    Research Scientist and Manager

    Research- and develop methods and systems to support formal methods- and verification of concurrent telecommunication systems

    TeleDanmark/Research & Development

    Validation and Formal Verification Manager

    Managing the validation and formal verification of selected parts of a many core processor including protocol components and vector processing with floating-point arithmetic.

    Intel

    IEEE

    ACM

    German

    Norwegian

    English

    Danish

    Swedish

    French

    PhD

    Computer Science

  • 1984

    TDR

    IBM

    Research

    develop

    and validate the CCITT CHILL compiler and the SDL-system as well as developing formal methods- and tools for telecommunication software

    TDR

    Caltech

    Computer Science

    Research- and further develop formal methods- and concurrency theory to enable practical

    computer supported verification of UNITY and C-programs that would support formally verified C-libraries to ensure higher quality software systems.

    Visiting Associate

    Responsible for creating and hiring the formal verification team assigned to verify that arithmetic

    cache coherence

    and other critical complex RTL.

    Intel

    Research Scientist in Formal Methods

    Security

    and Vulnerability Analysis

    Identify and implement technologies to use formal methods to detect- and prevent security vulnerabilities.

    Intel/CTG - Trusted Platform Lab

    Senior Verification Engineer

    TL

    Formal verification of critical

    complex components of the PowerPC 4 processor.

    IBM

    Researcher

    Portland

    Oregon Area

    Independent Researcher

    Responsible for creating

    hiring

    and developing formal verification techniques to verify arithmetic

    cache coherence protocols

    and other critical

    complex RTL.

    Intel

    Formal Verification Manager

    Responsible for the formal verification at the RTL-level of all arithmetic uops to avoid silicon escapes like the 1994 FDIV bug.

    Intel/DPG

  • PCIe

    Functional Verification

    Firmware

    Computer Architecture

    RTL design

    Logic Design

    EDA

    Embedded Systems

    Intel

    TCL

    Debugging

    Microprocessors

    VLSI

    Static Timing Analysis

    SystemVerilog

    ASIC

    Processors

    Verilog

    Formal Verification

    SoC

    Andersen

    Andersen

    Intel

    Caltech

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