Resume

• 2000

  MA/PhD

  Advisor: David I. August

  Computer Science

• 1992

  MBA

  Finance

  International Business Club

• 1986

  BSE/MS

  Computer Engineering

  TBP

  ACM

  Fencing Team

  College Bowl

  Symphonic Wind Ensemble

• 808

  us

• 587

  us

  jui-cheng su

  Welsh

  Spanish

  German

• 104

  us

  sandeep aggarwal

  gunes aybay

• Algorithms

  Cadence Virtuoso

  Computer Architecture

  Python

  Microprocessors

  FPGA

  Simulations

  VHDL

  ASIC

  Assembly Language

  C++

  Computer Science

  C

  Java

  Synopsys tools

  VLSI

  LaTeX

  Verilog

  Compilers

  Penry

  David

  Penry

  Princeton University

  Arm

  Brigham Young University

  ACC Microelectronics

  Bank One

  Sun Microsystems

  Princeton

  New Jersey

  Perform research into microarchitectural-level performance modeling of computer systems. Key\nachievements include:\n\n- Published techniques for specifying and generating microarchitectural simulators

  increasing simulator writing productivity by 10x and simulation speed by 3x.\n- Released version 1.0 of the Liberty Simulation Environment.

  Research Assistant in Computer Science

  Princeton University

  Provo

  Utah

  Lead research into microarchitectural-level performance modeling of computer systems

  high-level synthesis of accelerators for microarchitectural simulation

  and run-time adaptation of parallel programs. Teach computer architecture and systems

  digital VLSI design

  and compilers. Key achievements include:\n\n- Developed and published innovative techniques for:\no high-level synthesis of simulator accelerators.\no improved accelerator interfaces.\no specification of instruction-set simulators.\n\n- Frequent reviewer of papers dealing with microarchitectural performance modeling\n\n- Twice chair of the organizing committee for the Workshop on Architectural Research Prototyping.\n\n- Released FAMEbuilder

  a tool chain for high-level synthesis of accelerators for microarchitectural simulation.\n\n- Released version 2.0 of the Liberty Simulation Environment.\n\n- Developed and taught courses in computer architecture

  VLSI design

  and compilers.\n\n- Winner of NSF CAREER award.

  Associate Professor of Electrical and Computer Engineering

  Brigham Young University

  Sunnyvale

  CA

  Specify functionality

  develop RTL

  verify functional behavior

  perform place and route

  achieve timing closure and sign-off. Interface between design team and test

  OS

  and PROM development teams. Particpate in and/or lead post-silicon in-system bring-up. Key achievements include:\n\n- MAJC™ 5200 chip multiprocessor\n o Designed the PCI interface

  reset logic

  and clock controller from functional specification through sign-off.\n o Developed clock-crossing methodology.\n o Led in-system bring-up team.\n\n- Advanced PCI Bridge™ ASIC - lead designer\n o Developed architecture

  designed and validated RTL

  achieved timing closure

  performed all sign-off flows.\n o No bugs filed against chip post-fabrication.

  Member of Technical Staff/Staff Engineer - Hardware

  Sun Microsystems

  Develop tools for aggregating deposit information to feed asset/liability simulation.

  Bank One

  ARM

  Chandler

  Arizona

  Microarchitectural performance evaluation

  Principal Engineer

  Chandler

  Arizona

  United States

  Microarchitectural performance evaluation

  Senior Principal Engineer

  Arm

  Santa Clara

  California

  Develop RTL

  verify functional behavior

  achieve timing closure and sign-off for PC chipsets. Key achievements include:\n\n- Investigated and introduced RTL-based design methodology company-wide.

  Hardware Design Engineer

  ACC Microelectronics

  us